Single-chip 10.7 gb/s FEC codec LSI using time-multiplexed RS decoder.
Katsutoshi SekiKousuke MikamiM. BabaN. ShinoharaS. SuzukiH. TezukaS. UchinoN. OkadaY. KakinumaA. KatayamaPublished in: CICC (2001)
Keyphrases
- single chip
- reed solomon
- distributed video coding
- unequal error protection
- video codec
- bitstream
- forward error correction
- video quality
- error resilience
- low power
- turbo codes
- rate distortion
- high speed
- rate allocation
- packet loss
- video coding
- video transmission
- low complexity
- bit rate
- error resilient
- low cost
- bit errors
- error concealment
- error control
- coding scheme
- error correction
- transform domain
- wyner ziv
- multiple description coding
- channel coding
- frame rate
- image sensor
- compression algorithm
- macroblock
- error propagation
- wireless channels
- video streaming
- bit plane
- scalable video coding
- quality assessment
- scalable video
- embedded processors
- motion estimation
- motion compensation
- spatial domain
- low bit rate
- image quality
- wavelet coefficients
- image processing
- hardware and software
- video content
- visual quality
- subband
- peak signal to noise ratio
- coding efficiency
- coding method
- computational complexity