Two-level cache architecture to reduce memory accesses for IP lookups.
Sunil RavinderMario A. NascimentoMichael H. MacGregorPublished in: International Teletraffic Congress (2011)
Keyphrases
- memory access
- memory hierarchy
- data access
- main memory
- memory management
- cache misses
- access latency
- instruction set
- access patterns
- external memory
- memory subsystem
- processing units
- random access memory
- multithreading
- computing power
- cache conscious
- shared memory
- management system
- read write
- index structure
- query processing
- garbage collection
- data structure
- memory bandwidth
- data management
- virtual memory
- memory requirements
- real time
- computational power