A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS.

Maryam Fathi David K. Su Bruce A. Wooley

Published in: CICC (2010)

Keyphrases

power consumption
high speed
high power
low power
silicon on insulator
power management
cmos technology
nm technology
image sequences
power reduction
clock gating