A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA.

Jie Zhou Yong Dou Jianxun Zhao Fei Xia Yuanwu Lei Yuxing Tang

Published in: APPT (2009)

Keyphrases

fine grained
matrix inversion
coarse grained
hardware implementation
parallel architecture
monte carlo
access control
massively parallel
efficient implementation
least squares
hardware architecture
signal processing