Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs.
Francesco RestucciaMarco PaganiAlessandro BiondiMauro MarinoniGiorgio C. ButtazzoPublished in: ACM Trans. Embed. Comput. Syst. (2019)
Keyphrases
- high speed
- envy free
- input output
- field programmable gate array
- hardware implementation
- real time image processing
- resource allocation
- low cost
- real time
- data acquisition
- software implementation
- hardware architecture
- single chip
- verilog hdl
- hardware design
- game theory
- fiber optic
- systolic array
- lower cost
- digital signal
- signal processing
- power dissipation
- computer systems
- fpga implementation
- dedicated hardware
- gate array
- data sets