On average power dissipation and random pattern testability of CMOS combinational logic networks.
Amelia ShenAbhijit GhoshSrinivas DevadasKurt KeutzerPublished in: ICCAD (1992)
Keyphrases
- power dissipation
- power consumption
- low power
- cmos technology
- nm technology
- vlsi circuits
- digital signal processing
- chip design
- social networks
- power reduction
- pattern matching
- design methodology
- network structure
- high speed
- low cost
- flip flops
- real time
- finite state machines
- logic circuits
- network on chip
- image analysis
- case study