High Performance Hybrid Two Layer Router Architecture for FPGAs Using Network On Chip
Periyathambi EzhumalaiS. ManojkumarC. ArunP. SakthivelD. SridharanPublished in: CoRR (2010)
Keyphrases
- network on chip
- multi processor
- routing algorithm
- packet switched
- network simulator
- data transfer
- power dissipation
- distributed memory
- interconnection networks
- multi core processors
- single processor
- image processing
- program execution
- shared memory
- ad hoc networks
- field programmable gate array
- data flow
- network traffic
- routing protocol
- shortest path
- wireless sensor networks
- real time