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Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter.

José F. da RochaMarcelino Bicho Dos SantosJosé M. Dores CostaFloriberto A. Lima
Published in: IEEE Trans. Ind. Electron. (2008)
Keyphrases
  • low voltage
  • design considerations
  • power line
  • power management
  • random access memory
  • cmos technology
  • high speed
  • data center