Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.
Roberto AmmendolaAndrea BiagioniOttorino FrezzaFrancesca Lo CiceroPier Stanislao PaolucciAlessandro LonardoDavide RossettiFrancesco SimulaLaura TosorattoPiero ViciniPublished in: CoRR (2013)