A low power 1.25fJ/conv-step 12-bit SAR ADC with a high-efficient Dynamic Comparator.

Kaicong Dong Hua Fan Franco Maloberti Wei Zhou Jing Luo

Published in: ICECS (2023)

Keyphrases

low power
power consumption
low cost
single chip
high speed
low power consumption
high power
real time
wireless transmission
vlsi circuits
logic circuits
vlsi architecture