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Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes.

Shayesteh MasoumianRoel MaesRui WangKarthik Keni YerriswamyGeert Jan SchrijenSaid HamdiouiMottaqiallah Taouil
Published in: VLSI-SoC (2023)
Keyphrases
  • statistical analysis
  • data analysis
  • rapid development
  • pattern analysis
  • statistical modeling
  • neural network
  • x ray
  • shortest path
  • pattern mining
  • future development