FPGA Chip as a System Master for Hardware Aided Parallel Computing.
Jacek PierzchlewskiPawel SniatalaBlazej NowakowskiAndrzej RybarczykWojciech WencelPublished in: PARELEC (2006)
Keyphrases
- parallel computing
- field programmable gate array
- programmable logic
- low power consumption
- multithreading
- reconfigurable hardware
- massively parallel
- hardware architecture
- hardware design
- digital signal processing
- low cost
- parallel computation
- computing systems
- single chip
- high performance computing
- shared memory
- clock frequency
- high speed
- high end
- parallel architectures
- parallel programming
- computing platform
- parallel computers
- processing units
- hardware software
- computer architecture
- parallel machines
- parallel execution
- commodity hardware
- power dissipation
- stereo matching
- transactional memory
- general purpose processors