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A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology.
Wei-Zen Chen
Tai-You Lu
Yan-Ting Wang
Jhong-Ting Jian
Yi-Hung Yang
Guo-Wei Huang
Wen-De Liu
Chih-Hua Hsiao
Shu-Yu Lin
Jung Yen Liao
Published in:
VLSIC (2012)
Keyphrases
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cmos technology
phase locked loop
low power
clock frequency
power consumption
high speed
spl times
parallel processing
low voltage
high voltage
multipath
silicon on insulator
power dissipation
low cost
image processing
image sensor
real time
neural network