A 3.0V 12b 120 Msample/s CMOS pipelined ADC.
Sang-Min YooTae-Hwan OhHo-Young LeeKyung-Ho MoonJae-Whui KimPublished in: ISCAS (2006)
Keyphrases
- analog to digital converter
- single chip
- high speed
- image sensor
- low power
- power consumption
- low cost
- data flow
- circuit design
- analog vlsi
- power supply
- cmos image sensor
- delay insensitive
- sigma delta
- linear array
- dynamic range
- wide dynamic range
- rolling shutter
- cmos technology
- low voltage
- mixed signal
- parallel architecture
- vlsi circuits
- real time
- focal plane
- neural network
- database
- data structure
- case study
- search engine