Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block.
I-Chyn WeyChien-Chang PengFeng-Yu LiaoPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2015)
Keyphrases
- low power
- single chip
- power consumption
- logic circuits
- high speed
- low power consumption
- vlsi architecture
- gate array
- low cost
- power dissipation
- mixed signal
- wireless transmission
- digital signal processing
- data sets
- cmos technology
- hardware implementation
- efficient implementation
- design process
- fixed width
- peer to peer
- design methodology
- power reduction
- vlsi circuits
- ultra low power