Design and implementation of a Packet-in buffer system for SDN switches.

Shie-Yuan Wang Chun-Hao Chang Yi-Hsuan Hsieh Chih-Liang Chou

Published in: ISCC (2017)

Keyphrases

implementation issues
efficient implementation
design process
building blocks
high level synthesis
database systems
image quality
software architecture
packet loss
design decisions
circuit design
platform independent
buffer size
modular design
micron cmos