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A bit-interleaving 12T bitcell with built-in write-assist for sub-threshold SRAM.
Dashan Shi
Jia Yuan
Jialu Yin
Yulian Wang
Shushan Qiao
Published in:
IEICE Electron. Express (2022)
Keyphrases
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random access memory
design considerations
power consumption
adaptive threshold
case study
threshold selection
database
learning algorithm
artificial intelligence
search engine
decision trees
parallel processing
bit vectors