A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS.

Chang-Yuan Liou Chih-Cheng Hsieh

Published in: ISSCC (2013)

Keyphrases

low power
cmos technology
high speed
power consumption
low cost
synthetic aperture radar
nm technology
charge coupled devices
standard deviation
sar images
analog to digital converter
real time
parameter estimation
single chip
vlsi circuits
sea ice