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A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS.
Ik Joon Chang
Jae-Joon Kim
Sang Phill Park
Kaushik Roy
Published in:
IEEE J. Solid State Circuits (2009)
Keyphrases
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random access memory
design considerations
flip flops
cmos technology
embedded dram
low voltage
power consumption
low power
knowledge base
nm technology
image sensor
focal plane
parallel processing
low cost
protection scheme