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Implementation of a high-speed flash ADC for high-performance pipeline ADCs in an 180nm CMOS process.

Robert LoehrMarkus KempfFrank OhnhaeuserJuergen RoeberRobert WeigelAndreas Baenisch
Published in: ISPACS (2015)
Keyphrases
  • high speed
  • efficient implementation
  • parallel architecture
  • real time
  • low power
  • data mining
  • cost effective
  • high order
  • implementation issues
  • highly parallel
  • scientific computing