An all-digital delay-locked loop for high-speed memory interface applications.
Shih-Lun ChenMing-Jing HoYu-Ming SunMaung Wai LinJung-Chin LaiPublished in: VLSI-DAT (2014)
Keyphrases
- high speed
- gigabit ethernet
- low power
- low memory
- user interface
- user friendly
- high speed networks
- database
- memory usage
- computing power
- digital media
- phase locked loop
- windows xp
- memory size
- power dissipation
- frame rate
- memory requirements
- memory space
- feedback loop
- information processing
- video sequences
- database systems
- neural network
- real time