BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture.
M. Mottaghi-DastjerdiAli Afzali-KushaMassoud PedramPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2009)
Keyphrases
- low power
- vlsi architecture
- power consumption
- low cost
- high speed
- low power consumption
- mixed signal
- single chip
- cmos technology
- high power
- wireless transmission
- nm technology
- real time
- logic circuits
- digital signal processing
- floating point
- vlsi circuits
- signal processor
- hardware implementation
- power reduction
- gate array
- cmos image sensor
- ultra low power
- image sensor
- efficient implementation
- low complexity
- image processing