Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking.
Yirng-An ChenEdmund M. ClarkePei-Hsin HoYatin Vasant HoskoteTimothy KamManpreet KhairaJohn W. O'LearyXudong ZhaoPublished in: FMCAD (1996)
Keyphrases
- model checking
- word level
- asynchronous circuits
- language independent
- temporal logic
- formal verification
- automated verification
- model checker
- document images
- verification method
- machine translation
- finite state
- document analysis
- floating point unit
- formal specification
- floating point
- computation tree logic
- symbolic model checking
- sentence level
- viterbi algorithm
- character recognition
- word recognition
- epistemic logic
- n gram
- temporal properties
- transition systems
- bounded model checking
- concurrent systems
- word segmentation
- semantic roles
- image processing
- formal methods
- linear temporal logic
- massively parallel
- text retrieval
- text classification
- hidden markov models