Verification of CPS Based on Control Loop Using Model Checking.
Yoshitaka AokiShinpei OgataKazuki KobayashiHiroyuki NakagawaPublished in: APSEC (2018)
Keyphrases
- model checking
- control loop
- control scheme
- temporal logic
- closed loop
- automated verification
- control system
- model checker
- formal verification
- control strategy
- verification method
- temporal properties
- partial order reduction
- formal specification
- bounded model checking
- formal methods
- epistemic logic
- finite state machines
- pspace complete
- finite state
- symbolic model checking
- timed automata
- reachability analysis
- asynchronous circuits
- reactive systems
- transition systems
- concurrent systems
- computation tree logic
- real time
- abstract interpretation
- coalition logic
- artificial intelligence