Low-Power Multiplier Design Using Delayed Evaluation.

Gerald E. Sobelman Donovan L. Raatz

Published in: ISCAS (1995)

Keyphrases

low power
single chip
power consumption
high speed
low power consumption
low cost
logic circuits
vlsi architecture
digital signal processing
gate array
ultra low power
cmos technology
power dissipation
power reduction
vlsi circuits
design process
signal processing
video sequences
image processing