Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA.
Abner Corrêa BarrosVictor Wanderley Costa de MedeirosViviane Lucy Santos de SouzaPaulo Sérgio Brandão do NascimentoÂngelo MazerJoão Paulo Fernandes BarbosaBruno P. NevesIsmael SantosManoel Eusebio de LimaPublished in: SBCCI (2008)
Keyphrases
- hardware implementation
- fpga device
- efficient implementation
- dedicated hardware
- field programmable gate array
- software implementation
- fpga technology
- hardware architecture
- signal processing
- fpga implementation
- floating point
- hardware design
- parallel architecture
- xilinx virtex
- precision and recall
- general purpose
- type ii
- image processing algorithms
- verilog hdl
- computing systems
- reconfigurable hardware
- high precision