A low power, process invariant keeper for high speed dynamic logic circuits.

Rakesh Gnana David Jeyasingh Navakanta Bhat

Published in: ISCAS (2008)

Keyphrases

low power
high speed
logic circuits
low cost
power consumption
single chip
high power
gate array
digital signal processing
image sensor
vlsi circuits
functional decomposition
power dissipation
low power consumption
power reduction
mixed signal
wireless transmission
vlsi architecture
signal processor
real time