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A106nW 10 b 80 kS/s SAR ADC With Duty-Cycled Reference Generation in 65 nm CMOS.
Maoqiang Liu
Kevin Pelzers
Rainier van Dommele
Arthur H. M. van Roermund
Pieter Harpe
Published in:
IEEE J. Solid State Circuits (2016)
Keyphrases
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cmos technology
synthetic aperture radar
high speed
sar images
analog to digital converter
silicon on insulator
low cost
low power
metal oxide semiconductor
power consumption
image reconstruction
generation process
x ray
data aggregation
circuit design
single chip
nm technology
least squares
image processing