Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design.
I-Chyn WeyYi-Jung LanChien-Chang PengPublished in: Microelectron. Reliab. (2013)
Keyphrases
- low power
- cmos technology
- high speed
- low voltage
- power consumption
- mixed signal
- single chip
- low cost
- noise tolerant
- low power consumption
- vlsi architecture
- logic circuits
- power dissipation
- power reduction
- digital signal processing
- gate array
- power management
- ultra low power
- design considerations
- image sensor
- real time
- noisy data
- energy saving
- video camera
- hardware and software
- embedded systems
- digital images