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Implementation of a floating-point matrix-vector multiplication on a reconfigurable architecture.
Fabio Garzia
Claudio Brunelli
Davide Rossi
Jari Nurmi
Published in:
IPDPS (2008)
Keyphrases
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floating point
sparse matrix
reconfigurable architecture
square root
instruction set
sparse matrices
fixed point
graphics processing units
floating point arithmetic
fast fourier transform
similarity measure
systolic array
data model
sufficient conditions
rows and columns