An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture.
Chouki AktoufChantal RobachA. MarinescuGuy MazaréPublished in: J. Electron. Test. (1998)
Keyphrases
- massively parallel
- parallel computers
- processing elements
- vlsi implementation
- fine grained
- vlsi architecture
- parallel computing
- high performance computing
- parallel architectures
- graphics processing units
- floating point unit
- hardware implementation
- signal processing
- computational complexity
- parallel programming
- low power
- parallel processing
- instruction set
- higher order
- mesh connected