Login / Signup
A Low Complexity and a Low Latency Bit Parallel Systolic Multiplier over GF(2m) Using an Optimal Normal Basis of Type II.
Soonhak Kwon
Published in:
IEEE Symposium on Computer Arithmetic (2003)
Keyphrases
</>
low complexity
type ii
low latency
highly efficient
type i error
bit parallel
computational complexity
high throughput
motion estimation
high speed
databases
stream processing
pattern matching
virtual machine
response time
optimal solution
image sequences