A 252 Spins Scalable CMOS Ising Chip Featuring Sparse and Reconfigurable Spin Interconnects for Combinatorial Optimization Problems.
Yuqi SuJunjie MuHyunjoon KimBongjin KimPublished in: CICC (2021)
Keyphrases
- combinatorial optimization problems
- cmos technology
- low cost
- power dissipation
- analog vlsi
- low power
- high speed
- knapsack problem
- combinatorial optimization
- power consumption
- discrete optimization
- metaheuristic
- optimization problems
- ant colony optimization
- circuit design
- cmos image sensor
- chip design
- job shop scheduling
- single chip
- job shop scheduling problem
- focal plane
- low voltage
- image sensor
- traveling salesman problem
- continuous optimization problems
- parallel processing
- shortest path problem
- random access memory
- nm technology
- markov random field
- min cost
- search algorithm
- hardware implementation
- vehicle routing problem
- input output
- np hard
- genetic algorithm
- design methodology
- benchmark problems
- cost function
- silicon on insulator