FPGA Based Hardware Accelerator Design for Convolution Process in Convolutional Neural Network.

Ardian Dwi C Trio Adiono Nana Sutisna

Published in: ICEEI (2021)

Keyphrases

design process
hardware design
hardware architecture
convolutional neural network
embedded systems
hardware implementation
real time
field programmable gate array
low cost
case study
hardware and software
conceptual model
metamodel
hardware software
design tools
control unit