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A Compact Rail-to-Rail Class-AB CMOS Buffer With Slew-Rate Enhancement.
Chutham Sawigun
Andreas Demosthenous
Xiao Liu
Wouter A. Serdijn
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2012)
Keyphrases
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high speed
low power
image processing
low cost
buffer size
neural network
genetic algorithm