An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits.
Amitava ChatterjeeMahalingam NandakumarIh-Chin ChenPublished in: ISLPED (1996)
Keyphrases
- low voltage
- cmos technology
- power dissipation
- short circuit
- power consumption
- low power
- power management
- power line
- random access memory
- silicon on insulator
- digital signal processing
- chip design
- parallel processing
- mixed signal
- high speed
- design considerations
- energy saving
- finite state machines
- low cost
- reactive power
- computer systems
- fuzzy logic