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Design of a 4 GS/s radix-1.75 single channel pipeline ADC in 28 nm CMOS technology with foreground calibration.
Felix Lang
Markus Grozing
Manfred Berroth
Published in:
ISIC (2014)
Keyphrases
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cmos technology
low power
single channel
power consumption
multi channel
design process
power dissipation
low voltage
mixed signal
multiscale
multiresolution
high speed
feature points
parallel processing