A novel hybrid pass logic with static CMOS output drive full-adder cell.

Mingyan Zhang Jiangmin Gu Chip-Hong Chang

Published in: ISCAS (5) (2003)

Keyphrases

delay insensitive
logic circuits
low power
random access memory
low cost
chip design
high speed
modal logic
power consumption
input data
logic programming
automated reasoning
stem cell
data sets
proof theory
asynchronous circuits
power dissipation
computational properties
multi valued
rbf network