GRAPE-MPs: Implementation of an SIMD for Quadruple/Hexuple/Octuple-Precision Arithmetic Operation on a Structured ASIC and an FPGA.
Naohito NakasatoHiroshi DaisakaToshiyuki FukushigeAtsushi KawaiJunichiro MakinoTadashi IshikawaFukuko YuasaPublished in: MCSoC (2012)
Keyphrases
- hardware implementation
- hardware architecture
- xilinx virtex
- single chip
- highly parallel
- efficient implementation
- field programmable gate array
- signal processing
- software implementation
- circuit design
- parallel processing
- hardware architectures
- parallel architecture
- fpga implementation
- parallel implementation
- fpga technology
- hardware design
- real world
- pipelined architecture
- real time
- design methodology
- parallel algorithm
- structured data
- image processing
- parallel computing
- application specific
- low power
- associative memory
- dedicated hardware
- fpga device
- precision and recall