Combining watchdog processor with instruction cache locking for a fault-tolerant, predictable architecture applied to fixed-priority, preemptive, multitasking real-time systems.
Antonio Martí CampoyFrancisco Rodríguez-BallesterPublished in: ETFA (2019)
Keyphrases
- fault tolerant
- real time systems
- distributed systems
- fault tolerance
- memory hierarchy
- instruction set
- real time
- level parallelism
- embedded systems
- memory subsystem
- architectural model
- message passing
- scheduling problem
- multimedia
- distributed memory
- multithreading
- conceptual model
- load balancing
- computational intelligence
- fault isolation
- priority queue