Enable ++: A Second Generation FPGA Processor.
Hubert HöglAndreas KugelJozsef LudvigReinhard MännerKlaus-Henning NoffzRalf ZozPublished in: FCCM (1995)
Keyphrases
- single chip
- high speed
- digital signal
- parallel architecture
- systolic array
- gate array
- xilinx virtex
- fpga device
- hardware implementation
- field programmable gate array
- low power
- parallel processing
- hardware design
- low cost
- neural network
- real time
- efficient implementation
- real time image processing
- data acquisition
- computer systems
- parallel hardware
- signal processing