On the AER convolution processors for FPGA.
Alejandro Linares-BarrancoRafael Paz-VicenteFrancisco Gomez-RodriguezAngel Jiménez-FernandezManuel RivasGabriel JiménezAntón CivitPublished in: ISCAS (2010)
Keyphrases
- mesh connected
- parallel architecture
- field programmable gate array
- hardware implementation
- general purpose processors
- parallel processing
- real time image processing
- parallel algorithm
- array processor
- massively parallel
- high speed
- binary images
- parallel computing
- image processing
- address event representation
- general purpose
- single processor
- real time
- parallel computation
- artificial neural networks
- high end
- hardware architectures
- low cost
- dedicated hardware
- hardware architecture
- multiprocessor systems
- signal processing
- convolution kernel
- distributed memory
- fpga implementation
- processing elements
- parallel processors
- communication protocol
- multithreading
- parallel programming
- shared memory
- matrix multiplication
- parallel architectures
- power reduction
- embedded processors
- data acquisition
- single chip
- hardware design
- discrete fourier transform