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A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS.
Yudong Zhang
Xiaofeng Liu
Woogeun Rhee
Hanjun Jiang
Zhihua Wang
Published in:
ISCAS (2017)
Keyphrases
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cmos technology
mixed signal
low power
vlsi circuits
power consumption
low voltage
nm technology
circuit design
high speed
power dissipation
cmos image sensor
parallel processing
low cost
image sensor
silicon on insulator
metal oxide semiconductor
ultrasonic flow measurement
temperature control
room temperature