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FPGA Design and Performance Evaluation of a Pulse-Based Echo Canceller for DVB-T/H.
Giovanni Chiurco
Matteo Mazzotti
Flavio Zabini
Davide Dardari
Oreste Andrisano
Published in:
IEEE Trans. Broadcast. (2012)
Keyphrases
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real time
neural network
design process
hardware design
verilog hdl
data sets
image processing
low cost
single chip
e learning
case study
building blocks
design principles
low power consumption
hardware architectures