0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS.
Yong-Jun JoJu Eon KimKwang-Hyun BaekTony Tae-Hyoung KimPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2021)
Keyphrases
- low power
- high speed
- cmos technology
- single chip
- power consumption
- low cost
- nm technology
- vlsi circuits
- high power
- analog to digital converter
- digital signal processing
- low power consumption
- logic circuits
- mixed signal
- real time
- power reduction
- ultra low power
- image sensor
- wireless transmission
- power dissipation
- vlsi architecture
- frame rate
- low voltage
- delay insensitive
- cmos image sensor
- wide dynamic range
- infrared