Cambricon-U: A Systolic Random Increment Memory Architecture for Unary Computing.
Hongrui GuoYongwei ZhaoZhangmai LiYifan HaoChang LiuXinkai SongXiaqing LiZidong DuRui ZhangQi GuoTianshi ChenZhiwei XuPublished in: MICRO (2023)
Keyphrases
- real time
- pairwise
- computing power
- management system
- main memory
- architectural design
- memory space
- memory management
- memory requirements
- neural network
- associative memory
- uniformly distributed
- layered architecture
- memory size
- low memory
- memory hierarchy
- level parallelism
- parallel architecture
- systolic array
- design considerations
- random access
- memory usage
- network architecture
- software architecture
- data structure
- case study
- information systems
- databases