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A Low-Power CMOS Receiver for 1.25 Gb/s Over 1- mm SI-POF Links.
Carlos Sánchez-Azqueta
Cecilia Gimeno
Erick Guerrero
Concepción Aldea
Santiago Celma
Published in:
IEEE Trans. Ind. Electron. (2014)
Keyphrases
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low power
high speed
power consumption
low cost
single chip
cmos technology
high power
digital signal processing
wireless transmission
image sensor
vlsi circuits
low power consumption
mixed signal
vlsi architecture
real time
delay insensitive
power management
nm technology
gate array
ultra low power