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Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique.
Ji Li
Qing Xie
Yanzhi Wang
Shahin Nazarian
Massoud Pedram
Published in:
DATE (2015)
Keyphrases
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fine grained
power reduction
coarse grained
clock gating
power consumption
low power
access control
massively parallel
power dissipation
multithreading
power saving
cmos technology
high speed
data lineage
image processing
low voltage