Efficient implementation of sorting on multi-core SIMD CPU architecture.
Jatin ChhuganiAnthony D. NguyenVictor W. LeeWilliam MacyMostafa HagogYen-Kuang ChenAkram BaransiSanjeev KumarPradeep DubeyPublished in: Proc. VLDB Endow. (2008)
Keyphrases
- efficient implementation
- highly parallel
- hardware implementation
- single instruction multiple data
- parallel architectures
- active set
- processor array
- efficient processing
- management system
- multithreading
- software architecture
- parallel algorithm
- hardware architecture
- array processor
- real time
- graphics processing units
- level parallelism
- heterogeneous computing
- massively parallel
- parallel implementation