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Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors.
Megalingam Rajesh Kannan
M. Arunkumar
V. Arjun Ashok
Krishnan Nived
C. J. Daniel
Published in:
BAIP (2010)
Keyphrases
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memory subsystem
case study
power consumption
circuit design
user interface
design process
efficient implementation
prefetching
edge information
single chip
multithreading
memory hierarchy
caching scheme
embedded processors